1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor integrated circuit and, more particularly, to a method of manufacturing a semiconductor device using a plasma etching for the purpose of patterning a metal layer so as to form a conductive wiring by the metal layer which covers over an insulative layer formed on a semiconductor substrate.
2. Related Background Art
Hitherto, in a manufacturing step of a semiconductor device, there is a case where a conductive wiring is formed by a conductive layer laminated on a semiconductor substrate through an insulative layer. In the case where an etching process for forming the conductive wiring is performed by using, for example, a high density plasma, an electric potential difference due to charge-up is caused between the conductive layer which is subjected to a plasma gas and the semiconductor substrate arranged through the insulative layer under the conductive layer. Therefore, in the case where a gate electrode of a semiconductor device such as an MOS transistor has been formed under the conductive layer, if the excessive potential difference is caused, there is a case where a thin gate oxide film under the gate electrode is damaged.
As a conventional technique for preventing such a damage caused by the charge-up, for example, there is a technique disclosed in JP-A-10-189501.
According to the conventional technique, a conductive layer and a semiconductor substrate are electrically connected through a predetermined conductive path serving as a fuse mechanism. For the fuse mechanism, a plurality of shallow grooves are formed on the conductive layer, that is, in a contact portion of the conductive layer and the semiconductor substrate at intervals of about the minimum working dimensions which are specified by a design rule.
According to the fuse mechanism, the conductive layer and the substrate are electrically connected through bottom portions of the shallow grooves of the conductive layer, that is, fuse portions. At the time of an etching process for the conductive wirings, the bottom portions of the shallow grooves of the conductive layer, that is, fuse portions are also subjected to the etching process. In the fuse portions, however, the etching operation progresses relatively slowly due to a conventionally well-known loading effect. For such a period of time, since the electrical connection between the conductive layer and the substrate is maintained, electric potentials of both of them are almost equal, so that the charge-up damage is prevented.
According to the fuse mechanism, after completion of the conductive wirings by the conductive layer, the fuse portions are separated due to the progress of the etching function, so that the electrical connection between the conductive layer and the substrate is disconnected.
According to the fuse mechanism of the conventional technique, however, in order to certainly maintain the electrical connection until the conductive wirings are completed, it is necessary to design the fuse portions including the shallow grooves of a small width which provide such characteristics as mentioned above. However, it is not easy to design such a fuse mechanism.
It is also necessary to hold a pattern region of the fuse mechanism and, since an effective area adapted to form the conductive wirings of the conductive layer is narrowed for such a purpose, it is disadvantageous when designing the pattern of the conductive wirings.